The subject matter described herein is concerned with methods of fabricating semiconductor devices, more particularly to methods for performing a damascene process in fabricating a semiconductor.
Generally, semiconductor devices have electrical components, such as transistors, resistors, capacitors and interconnections connecting them, and insulating layers structurally supporting and electrically isolating the electrical components. In recent years, as the integration of semiconductor devices has increased, the electrical components required for fabricating such devices have become smaller in size and need to be positioned in very close proximity to each other. However, because the smaller size of electrical components requires reducing the cross-sectional areas of interconnections, the result is an increase in the electric resistance of such interconnections. In addition, undesirable RC delay and interference result from the increased densification and physical proximity of the electrical components. The increase in the electric resistance of interconnections, the RC delay and increased interference are among the major factors limiting the operation speed of modem semiconductor devices.
To overcome these troubles, it has been proposed that copper of low electrical resistance be used as a material for semiconductor electrical interconnections, and also that a low-k dielectric material be used as an intermetal dielectric (IMD). As is well-known, the electric conductivity of copper is higher than that of aluminum, which has been conventionally used for semiconductor interconnections. The higher electric conductivity of copper can prevent a reduction in data processing speed and an increase in power consumption, which are caused by the RC delay. In addition, because the phenomenon of electromigration (EM), which is known as a major problem of aluminum interconnections, can be effectively suppressed by using copper, semiconductor devices employing copper interconnections are free from the product defect and the process restriction caused by EM. Consequently, semiconductor devices employing copper interconnections have a higher yield than semiconductor devices employing aluminum interconnections.
Since, as is well known in this art, copper is unsuitable for carrying out vapor deposition and dry etching processes in semiconductor fabrication, a damascene process is needed in order to use copper as a material for semiconductor interconnections. More specifically, the copper interconnection can be formed by a damascene process that comprises the sequential steps of: forming an interlevel dielectric pattern with an opening on a semiconductor substrate, forming a copper film over the dielectric pattern and filling the opening, and etching the copper film by means of a chemical-mechanical polishing (CMP) technique. By this method, an interlevel dielectric pattern is formed comprising a low-k dielectric (k is a dielectric constant), as explained above. But, because the low-k dielectric thus formed is typically weak in terms of mechanical quality, scratches are easily formed on the top surface of the interlevel dielectric pattern during the CMP step. The scanning electron microscope (SEM) picture of FIG. 1 shows such scratches formed during the CMP step.
Such scratches make it difficult to remove conductive materials, which are deposited by subsequent processing steps, or metallic residues remaining from the CMP process. In this sense, the scratches are an important negative factor that causes a leakage current between interconnections and furthermore deteriorates the reliability of the semiconductor product. While the use of a passivation film on the interlevel insulation film pattern is sometimes helpful in reducing the problems caused by the scratches, the additional formation of the passivation film increases the number of processing steps and the cost for manufacturing the semiconductor product. Further, this approach also requires an additional operation for subsequently removing the passivation film used in minimizing the RC delay problem. Moreover, if the passivation film is removed by the CMP operation, the problems related to the formation of scratches is not satisfactorily overcome.